As computer software applications continually become more complex, and as multiple applications run simultaneously (e.g., multitasking), the computers on which the software applications run must increasingly become faster to avoid processor delay times and other time lags that can be annoying to a computer user. A significant limitation on the computer's operating speed is the time required to transfer data between the processor and a memory circuit. Typical memory circuits, such as dynamic random access memories (DRAMs), include a large number of memory cells arranged in one or more arrays, each array having rows and columns. The memory cells provide locations at which the processor can store and retrieve data including program instructions.
The more quickly the processor can access the data within the memory cells, the more quickly it can perform calculations or execute software applications using the data. As the need grows for decreased data access times, new types of memory devices are being developed. For example, certain memory devices allow data from groups of memory cells to be output from a DRAM based on an initial request from the processor. Page mode DRAM or burst extended data out (BEDO) memory allows a large amount of data to be rapidly output to a processor, thereby improving the effective speed of the memory device.
To further improve the access time to memory cells, synchronous DRAM (SDRAM) devices have been developed. When a typical DRAM device receives a read or write command and an address, the data transfer must be performed in its entirety before the device can accept another command Consequently, subsequent commands or processor operations are delayed by the entire duration of the first data transfer. Because data transfer typically involves several steps and each step takes time, the overall time to perform the first data transfer in a DRAM device may be significant.
In SDRAM devices, operations are "pipelined" in that each of the several steps required to transfer data is performed according to a specific timing sequence. The timing sequence is established relative to a clock signal, typically an external clock signal in the computer that controls the processor. As a result, both the processor and the SDRAM are synchronized under the same clock. Therefore, in theory, if the clock frequency is increased, the data transfer to and from the SDRAM can be similarly increased.
As the clock frequency increases, the time required to perform each of the various commands and steps to transfer data to and from the memory device decreases. Current SDRAM devices can operate at a clock speed of 100 MHz (equal to a period of 10 nanoseconds). All of the data transfer steps to read data to, or write data from, the SDRAM can be performed in approximately 9 nanoseconds. Thus, at a clock speed of 100 MHz, there is a 1 nanosecond margin of error. Such a tiny margin of error requires that the SDRAM device perform substantially flawlessly, with essentially no margin of error for delays within the device.
It would be desirable to be able to operate the SDRAM device at a slower clock speed, and thereby provide a greater margin of error for the device. Indeed, most computer designers and other engineers employing SDRAM devices employ such devices in systems operating at a variety of clock speeds. Therefore, it also would be desirable to have a SDRAM device capable of operating at both a fast clock rate (approximately 125 MHz) as well as slower speeds (66 MHz or less), to compensate for various external clocks with which the SDRAM device may be employed.